1. Field of the Invention
The present invention relates to a random access memory device and a method of controlling the random access memory device in pipe line page mode.
2. Description of the Prior Art
Conventionally, there have been proposed various kinds of high speed operation modes suitable for memory devices provided with a dynamic random access memory (DRAM). The page mode is well known as one of these modes.
In this page mode, after one word line corresponding to a row address has first been activated, in order to read a data from the column corresponding to a column address, only the column address is changed to sense data stored at the respective cells connected to the word line, so that the sensed data can be read. In other words, the column addresses are changed by keeping the row address unchanged. FIG. 5 is a timing chart showing the timing of control signals for switching the data read/write operations in this page mode. Further, in the following description, VIH indicates that the input signal level is at "H"; VIL indicates that the input signal level is at "L"; VOH indicates that the output signal level is at "H"; and VOL indicates that the output signal level is at "L", respectively.
FIG. 5 shows a so-called high speed page mode in which a data dA is read from an address A, and an input data iB is written at the address B. Further, in FIG. 5, the time interval between the current rise time and the succeeding rise time of a CAS (column address strobe) signal is determined as one cycle. In this one cycle, a series of data are transferred to the cells and written therein, and further, a series of the written data are transferred from the cells to complete the data read operation.
First, in the data read operation, the access operation starts from the address transition after the rise time of the CAS signal, and data are outputted during the time interval of tAA or tCAC after the fall time of the CAS signal. In the data write operation, input data iB held for a predetermined constant time interval tW at the fall time of the CAS signal are internally written to the column selected in the address transition. Here, the data read or write operation is determined by the status of a WE (write enable) signal at the fall time of the CAS signal. In more detail, the data read operation is determined when the WE signal is at a high level, and the data write operation is determined when the WE signal is at a low level. Further, in FIG. 5, the portions of the address signal shown by hatched lines indicate a so-called "don't-care" status in which the address status is not related to the operation.
The control method such that high speed page mode operation is executed at a shorter cycle time interval by continuously executing the high speed page mode as described above over two cycles has been proposed, which is referred to as a pipe line page mode. In this pipe line page mode, there exists such a feature that the operation portions corresponding to the routes for the transfer sequence are separated to execute the data transfer operation.
The data transfer sequence operation in the pipe line page mode will be described hereinbelow in further detail with reference to FIGS. 6 to 11. FIGS. 6 and 7 typically show the data routes from the bit line to the data input and output, in which FIG. 6 corresponds to data read operation and FIG. 7 corresponds to data write operation, respectively.
In the case of data read operation, a bit line A is connected to a route Al between a column select gate 1 and an intermediate sense amplifier 2 via the column select gate 1. The column select gate 1 is selected by a column address signal to transfer a data. The intermediate sense amplifier 2 amplifies the transferred data and further transfers the amplified data through a route A2 to an output buffer 3. The output buffer 3 receives the transferred data and outputs the received data to an output terminal 4 through a route A3 in sync with the fall time of the CAS signal.
In the case of the data write operation, a data inputted to an input terminal 5 is latched by an input buffer 6 in synchronism with the fall time of the CAS signal, and the signal level thereof is converted. The output of the input buffer 6 is transferred to an intermediate buffer 7 through a route al for amplification. The amplified data is further transferred to a route a2. Since a column select gate 8 for connecting the route a2 with a bit line a has already been selected by a column address, the data is transferred from the bit line a to the memory cell through the route a3 and then written therein.
FIGS. 8 and 9 are examples of the timing charts where the flow time of data is allocated in data read operation in the cycle determined by the CAS signal, in which FIG. 8 shows the case of the high speed page mode and FIG. 9 shows the case of the pipe line high speed page mode, respectively.
In FIG. 8, immediately after the address transition status has been detected by an address transition detector (ATD, not shown), the process Al is activated and further the process A2 is automatically activated. Here, the process A3 is activated at the fall time of the CAS signal.
The dot lines shown in FIG. 8 indicate that the address transition is effected again before the fall time of the CAS signal. In this case, since the process from A1 is resumed at the address transition start time point and further the CAS signal has already fallen before the A2 is activated, the process progresses in sequence in the order of A1, A2 and A3.
FIG. 9 shows the case where a shorter cycle time can be realized by operating the respective processes of A1, A2 and A3, respectively in pipe line fashion. For instance, if the process Al ends during the process of reading the column address A, this data transfer route portion can be used at the process for reading the succeeding column address B. Therefore, it is possible to effectively use the data transfer system by starting the process of B1 to B3 for the address B immediately after the process A1 ends. However, in the case of the pipe line page mode, the address setting and the CAS signal cycle during which the address data is outputted are offset from each other one by one of the CAS signal cycle. As described above, in this mode, the access started by the address transition can be defined from the previous cycle (onecycle before the current cycle). Further, as understood by this example, in order to realize the pipe line page mode, it is necessary that the data routes corresponding to the respective process are separated independently.
FIGS. 10 and 11 show the timing charts where the data write time is allocated, in which FIG. 10 indicates the case of the high speed page mode, and FIG. 11 indicates the case of the pipe line high speed page mode.
With reference to FIG. 10, either one of the data read operation and the data write operation is discriminated at the time when the CAS signal falls in the CAS signal cycle to execute the data write operation. Therefore, here, if the data write operation is first assumed to be executed for instance, the data read operation is started on the basis of the previous address transition. Thereafter, when the data write operation is discriminated at the fall time of the CAS signal, the data read operation is stopped at this moment and the data write operation is started. In FIG. 10, the data write operation is executed as a series of operations from al to a3. The dot lines indicate that the address transition is delayed, which teaches that although the data write operation starts before the data read operation does not sufficiently progress, it is well understood that the sequence al, a2 and a3 of the data write operation started at the fall time of the CAS signal will not change.
With reference to FIG. 11, since data is decided at the data transfer route portion of the sequence a2 at the time when the operation of the sequence a3 starts, it is possible to utilize the data transfer route portion of the sequence al for the data write operation of another column address, after the data has been transferred from a1 to a2. Therefore, by executing pipe line operation, the data write operation can be executed during a shorter cycle. In other words, the sequence a3 is activated in the succeeding CAS signal cycle after the CAS signal cycle during which a data is written, in parallel to the data write operation to the bit line of the address b.
In the prior-art pipe line high speed page mode, however, since there exists no idle time usable for another operation in the data transfer route, it is impossible to mix the data write operation with the data read operation. Therefore, as is the case of the page mode shown in FIG. 10, it is impossible to set a certain CAS signal cycle to any one of the data read operation and the data write operation at the head of the cycle thereof. In the data write operation in this pipe line page mode, although there exists no problem in that the CAS signal cycles of the address and the data are offset from each other as is the case of data read operation, since the data is written in the cell at the succeeding cycle, the CAS signals of two cycles are inevitably required.
As described above, in the prior-art pipe line high speed page mode, since the data transfer routes are superimposed upon each other at the respective cycles and therefore the cycle during which an address is written is different from the cycle during which a data is read between the data read and write operations, it has been difficult to mix the data read and write operations during the same page mode cycle.
Furthermore, the pipe line control is disclosed in U.S. Pat. No. 4,597,061 (Jun. 24, 1986). In this Patent document, however, the concept is such that the latching and then outputting a data or an address is applied to a SRAM, and nothing is disclosed of how to execute the pipe line page mode control by use of the DRAM, in practice.